In the semiconductor integrated circuit (IC) industry, there is a continuing demand for higher circuit packing densities. This demand of increased packing densities has led the semiconductor industry to develop new materials and processes to achieve sub-micron device dimensions. Manufacturing IC's at such minute dimensions adds more complexity to circuits, and the demand for improved methods to inspect IC's in various stages of their manufacture is ever present.
Although inspection of such products at various stages of manufacture is very important and may significantly improve production yield and product reliability, the increased complexity of IC's increases the cost of such inspections, both in terms of expense and time. However, if a defect can be detected early in production, the cause of the defect can be determined and corrected before a significant number of defective IC's are manufactured.
In order to overcome the problems posed by defective IC's, IC manufacturers sometimes fabricate semiconductor defect test structures (test structures). Such test structures are dedicated to defect analysis. The test structures are fabricated such that they are sensitive to defects that occur in IC product, but are designed so that the presence of defects is more readily ascertained. Such test structures are often constructed on the same semiconductor substrate as the IC products. One place to hold test structures is the scribe line. A scribe line is an area at the edge of the die where the die will be separated from each other by a diamond saw. Since the scribe line occupies a very small area, the scribe line can only hold a very limited number of test structures. Furthermore, since the test structures need probing when they are tested, most of the scribe lines are occupied by probe pads, which are located on a top metal layer of a chip.
With the development of deep sub-micron technology, there exists a need to place more test structures in both a test chip and a product chip such as RapidChip™ developed by LSI Logic Corporation, and the like, since previous Q-chip (Qualification-chip) qualification cannot guarantee the later tape-out being successful as well. However, real estate in a semiconductor integrated circuit is precious and limited. Thus, it would be desirable to provide a method and apparatus for placing more test structures in a semiconductor integrated circuit.